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IEEE std 1666 SystemC Support




V2SimTM and RaceCheckTM Provide Native Support for IEEE SystemC and PSL Languages

June 2, 2008

Dynetix state-of-the-art V2SimTM and RaceCheckTM products now provide native support for IEEE SystemC (std 1666) and PSL  (Property Specification Language, IEEE 1850) languages. With these new capabilities, both products can now seamlessly verify large-scale, deep submicron HDL and ESL designs, coded in any combination of VHDL, Verilog, SystemVerilog, PSL and SystemC languages. More importantly, Dynetix patented advanced  multithreaded simulation and race logic audit technologies can now be applied to any multi-billion gate SoC, ASIC, FPGA and customer IC designs that are coded in any combination of IEEE standard HDL and ESL languages.

According to Terence Chan, Dynetix products are designed from the ground-up to be language-neutral, so that Dynetix patented technologies could  be used in all large-scale SoC, ASIC, FPGA, and custom IC development by customers. The support of the IEEE PSL and SystemC languages completes Dynetix goal to provide customers with the most advanced and powerful design verification tools that will accept all design languages they use, and can utilize all the multi-CPU, multithreaded computing resources they have, to drastically reduce their IC verification time and time-to-market.   

Both the RaceCheckTM and V2simTM products are now in production release.

For More Information Contact:

Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568
Tel: 408-836-9654
FAX: 925-828-7843
Internet: info@dynetix.com





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