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US Patent 9032266




US Patent and Trademark Office Issued a US patent to Terence Chan

US Patent No. 9,032,266

May 12, 2015

US Patent and Trademark Office has issued a US patent 9,032,266 to Terence Chan, CEO and President of Dynetix Design Solutions

The patent covers advanced multithreaded mixed-HDL/ESL concurrent fault simulation technologies, for large-scale deep submicron integrated circuit designs, on industrial standard symmetrical multiprocessor (SMP) platforms. Specifically, the new patent technologies can be implemented in stand-alone fault simulators or be incorporated into automatic test generation (ATG) products, so that testing of billion-gate integrated circuits that take days and weeks to complete by the current commercial tools may now be done in hours. This aids customers time-to-market and ensure their products with highest quality. According to Terence Chan, the patent helps Dynetix Design Solutions maintains its technical leadership in the digital and mixed-signal IC verification market.


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Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568 USA
Tel: 925-833-7851
Internet: info@dynetix.com





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