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RaceCheck Beta Release




Dynetix Design Solutions announces the beta-release of the State-of-the-Art RaceCheckTM program

Nov 1, 2005

Dynetix Design Solutions announced the immediate release of the RaceCheckTM program to aid HDL/ESL designers to audit race logic in users' IC circuits, and to improve their products quality and time-to-market.

Race logic occurs when IC logic constructs behave differently when they are being executed in different orders, as it would happen if those logic constructs are operated upon concurrently in physical IC chips, or when they are simulated by different HDL simulators which evaluate IC logic in different orders. Examples of race logic includes simultaneous driving of incompatible signal states, by different logic blocks, to a register object; the concurrent assignment and reference of a signal or register object by different logic blocks; or the concurrent execution of tasks which access and modify the same set of external signal or register objects. Race logic cannot be detected via simulation or formal logic verification. RaceCheckTM is the industrial-first design verification tool dedicated to auditing hard-to-detect race logic in large-scale IC designs.  RaceCheckTM complements advanced HDL simulators (e.g., V2SimTM) formal logic verification tools  and static timing analyzers to aid users achieve 100% functional coverage of their IC products and time-to-market.

The patent-pending state-of-the-art race logic checking technologies, which have been implemented in RaceCheckTM,  includes both a static race logic checker and a dynamic race logic checker. 

The static race logic checker exhaustively analyzes a HDL/ESL circuit based on the structural and timing description of the design. No test vector is needed. The results are all possible race conditions that may manifest themselves in physical chips. The static race logic checker specifically takes into account the timing delays of signal activities to filter out false race conditions.  

The dynamic race logic checker, which uses the advanced V2SimTM HDL simulation engine, performs a full-timing and event-driven simulation of a user HDL/mixed-signal circuit, and checks for race conditions on all circuit elements at every simulation time point. The dynamic race logic checker reveals race conditions that are most likely to manifest in actual IC chips, and thus its results are precise and accurate.

The combined use of the static and dynamic race logic checker programs yields both exhaustive and precise race logic analysis of users HDL/ESL circuits. RaceCheckTM supports IEEE Verilog, VHDL, SystemC, PSL and SystemVerilog design languages in a single kernel, and it can operate in either 32-bit or 64-bit mode. RaceCheckTM supports deep submicron ASIC, SoC, FPGA, and custom IC design methodologies. 

The RaceCheckTM product is available immediately on Windows-XP, Linux and Sun Solaris platforms.


For More Information Contact:

Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568 USA
Tel: 925-833-7851
Internet: info@dynetix.com





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