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IEEE APCCAS-06 Presentation




Terence Chan Presented RaceCheckTM Technologies at the IEEE APCCAS-06 Conference 

June 10, 2007

Terence Chan, the President and CEO of Dynetix Design Solutions, presented a technical paper on the RaceCheckTM  technology for nanometer SoC designs at the IEEE Asian Pacific Conference on Circuits and Systems 2006 (APCCAS-06) in Singapore, on December 5th, 2006. The paper was based on Terence Chan's  patent-pending (US and international) race logic analysis technologies. 

According to Terence Chan, race logic is an important category of design errors that is commonly over-looked by IC designers. If race logic is not caught and fixed during an IC design functional verification stage, the corresponding IC chips may manifest intermittent failures on the field, and could render product recall. Current EDA tools do not provide adequate coverage for race logic, and some may even mask race logic effects to give designers a false sense of confidence of  their IC designs' functional coverage. RaceCheckTM is designed solely to audit hard-to-detect race logic in large-scale deep submicron IC designs (e.g., SoC's). It complements V2imTM and other EDA design verification tools to aid users achieve true 100% functional coverage of their IC products. 

The RaceCheckTM product is now in production release by Dynetix Design Solutions.

For More Information Contact:

Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568 USA
Tel: 925-833-7851
Internet: info@dynetix.com





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