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FOR IMMEDIATE RELEASE

US PTO Issues Patent US 7,757,191 To Dynetix Design Solutions

US Patent No. 7,757,191

July 15, 2010

US Patent and Trademark Office has issued a patent US 7,757,191 to Dynetix Design Solutions Inc. This is a continuation patent for the US patent 7,334,203. The two patents depict state-of-the-art static and dynamic race logic analysis technologies for large-scale SoC, ASIC, FPGA and custom IC designs. The new patent depicts more advanced technologies for auditing concurrent assignment race logic, concurrent assignment and reference race logic, advanced filtering of concurrent invocation race of HDL/ESL system functions/tasks, and advanced detection of race logic on inter-process communication (IPC) objects in ESL designs. 

The advanced race logic audit technologies of US 7,334,203 and US 7,757,191 have been implemented in RaceCheckTM

According to Terence Chan, the CEO and President of Dynetix Design Solutions Inc, the patented advanced race logic audit technologies and RaceCheckTM are essential in helping large-scale, deep submicron IC designs to achieve comprehensive functional coverage, improve design quality and aid time-to-market. RaceCheckTM compliments V2simTM to aid reduction of any new deep submicron IC product development time by over 30% and to achieve 100% functional coverage.

 


For More Information Contact:

Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568
Tel: 925-833-7851
Internet: info@dynetix.com


 

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